Staff IC Layout Engineer

Since 2021 our team has been listed every year in the “Top 100 Startups worth watching” in the EE Times, and our technology breakthroughs have been featured in The Telegraph, BBC and the New Statesman. Our founders are internationally renowned researchers from UCL and Oxford University who have pioneered the development of qubits and quantum computing architectures. Our chairman is the co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation. We’re backed by a team of top-tier investors, and we have recently closed our Series C funding of $160 million.

We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians and software engineers to create a unique, world-leading team, working together closely to maximise our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology.

Our team of 100+ is based in Oxford and London, with a centre of mass in our Islington lab.

The IC Team is responsible for the design and test of the integrated circuits which operate at deep-cryogenic temperatures and interact with the qubits. This role is a unique chance to work at the bleeding edge of technology development, developing new innovative circuits to tackle the engineering challenge of implementing a large scale quantum computer in silicon. You will be a key part of a multidisciplinary team, and will be involved in all the aspects of IC design cycle from initial concept to volume production.

This is a rare and exciting opportunity to be an early employee at a start-up shaping the future of quantum computing, and in particular to form a new team within the company. There are vast opportunities for professional growth and to make an impact within the company.

As a Staff IC Layout Engineer, the position will suit a multidisciplinary profile with expertise in Analog IC Layout primarily and CAD management secondarily. No quantum experience required, but curiosity and a strong desire to learn and input into a brand-new technology area are critical.

• Responsible for the delivery of analog-on-top top-level layouts, including IO management, floor-planning, digital integration, and routing management.
• Block-level layout implementation and PEX optimization of RF transceiver blocks and high-precision Analog blocks
• Development of custom PDK elements from scratch including Schematic and Layout SKILL PCells, and custom DRC and LVS decks.
• Management of internal and external layout resources.
• Document own work and perform layout reviews with other team members

• Industry degree qualification and at least 10 years of experience in Analog and RF nmCMOS Layout
• Expert-level knowledge of RF layout techniques.
• Proficiency in Cadence Virtuoso Layout XL
• Proficiency in DRC, LVS, & Parasitic Extraction with Siemens Calibre
• Proficiency in PCell development.
• Proficiency in DRC and LVS deck writing.
• Team player with a collaborative mindset
• Excellent verbal and written communication skills

• Proficiency in EM simulations.
• Proficiency in SKILL++
• Proficiency in IC package design
• Knowledge of MOS Quantum Dots Physics.

• Be part of a creative, world-leading team

• Competitive salary and share options scheme

• Contributory pension scheme

• Life Assurance

• Cycle-to-work Scheme

• Flexible working

• Central London location