Welcome to Codasip

We believe Codasip is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient CPU cores from scratch, and our own automated proprietary tools to fully customize them. We give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.

Our processor cores are based on the RISC-V open architecture. The potential for customizing RISC-V is unlocked with the Codasip Custom Compute approach: our unique architecture description language, CodAL, and the powerful automated processor design tool, Codasip Studio. These are at the heart of our unique and groundbreaking RISC-V processor solutions.

Founded in 2014, we've grown into a thriving and talented global community. Our IP engineering teams work from offices spread across Europe, including our first and largest design center in the beautiful city of Brno, Czechia. Across Europe, we already have design teams in Cambridge, Bristol, Munich, Villeneuve-Loubet, Barcelona, Thessaloniki, Heraklion and Athens. The Codasip team is also based close to its customers, which means we have dedicated sales and application engineers in the USA, Japan, Korea, and China.

Codasip is a private company backed by well-funded EU grants. Our products are already making a real impact, with billions of devices already in the market powered by our processor IP and tools.

Locations: Czech Republic (Brno/Prague)

Department: Czech Design Center

Employment Type: Full-Time

Experience: Mid-senior

YOUR ROLE:

We’re looking for a Hardware Design Engineer to join us either in the Brno or Prague office. The job duties consist of but are not limited to:

• Contribute and responsible for the development of the RISC-V processors and extensions:
• microarchitecture definition
• block specification
• component design
• design synthesis and analysis of its results
• Designing generic solutions for process automation
• Processor development using the Codasip Architectural Language (CodAL)
• Ensuring the design meets its PPA targets
• Working closely with the verification team on verification planning, debugging, and final sign-off

The following skills are essential to perform the job duties

• Knowledge of modern CPU architectures (ideally RISC-V) and micro-architectures, or track record in complex pipelined designs.
• Active usage of at least one Hardware Description Language (preferably SystemVerilog)
• Understanding of physical implications when designing at a higher level of abstraction (digital design synthesis and implementation flow).
• Practical expertise in versioning tools (preferably git)
• Proficiency in scripting languages (Shell, Python, Tcl)
• Ability to work with compiler/software components.
• Practical usage of Linux
• Communicative English as English is the main language of Codasip

NICE TO HAVE:

• Hands-on experience with HW simulators and implementation tools
• Experience with SIMD architectures
• Active interest in the field and self-education
• Experience with Formal Verification concepts

Want to be an architect of ambition? Join Codasip

At Codasip we are committed to fostering a creative and collaborative work environment. Codasippers have the freedom to explore original ideas and experiment with new techniques. We believe in the benefits of cross-departmental collaboration and encourage sharing to build awareness throughout the teams. This enables you to add value through variety in your work.

When you join Codasip, you become part of a motivated team of self-starters where your ideas are appreciated and your voice is heard. We strive to create an environment where your ambition can flourish and your career can reach new heights. So, come and join our team of architects of ambition. We can't wait to see what you'll achieve at Codasip.

RISC-V core for power-efficient applications

CodasipStudio

Codasip- Risc-V processors

CodAL language

Přednášky FIT VUT

Design for differentiation: architecture licenses in RISC‑V

Building a Swiss cheese model approach for processor verification

Efficient verification of RISC-V processors – Technical paper

You will be working on:

https://codasip.com/products/low-power-embedded-risc-v-processors/l110/#